OptimizeHPC

Code Optimization and Auto-Tuning for Simulation on Heterogeneous Parallel Architectures

Recent trends in hardware advancements pose a challenge to the development of simulation software. In particular, since the saturation of the CPU clock frequency around 2005, hardware has diverged in terms of the number of cores, parallel units and accelerator cards to ensure the acceleration of about a factor 100 every five years (Moore’s law). Especially the latter ones prevent hardware-independent programming, as they require custom-tailored code. And even performance-optimized code for a certain platform will typically not show optimal behavior on a similar system with slightly different parameters. Program-specific parameters have to be determined, such as the number of parallel threads, the size of messages for communication, or the number of bytes fetched from memory in a coalesced manner.

This image shows Miriam Schulte
Prof. Dr. rer. nat. habil.

Miriam Schulte

Head of Institute

This image shows Malte Brunn
M.Sc.

Malte Brunn

Researcher

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